As integrated circuits become more complex, process integration requires several processes. Also, the continuing miniaturization, of electronic devices requires that interconnects be positioned at multi levels in the device. For copper, the requirement of several layers of metallization becomes increasingly complicated by the associated requirement of etch stop and diffusion harrier structures at each level.
In damascene processing, the interconnect structure or wiring pattern is formed within trenches or vias formed within a dielectric film. Using known techniques a photoresist material is used to define the wiring pattern. The patterned photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. The etched openings are used to define wiring patterns in the dielectric layer. These wiring patterns can extend from one surface of the dielectric layer to the other surface of the dielectric layer. Alternatively, the wiring patterns can be confined to a single layer, that is not extend to the opposite surface of the dielectric layer.
The wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination thereof. A harrier layer is typically used to minimize atomic diffusion of the conductive metals into the dielectric.
In the single damascene process, via openings are provided in the dielectric layer and filled with a conducting metal, which is often referred to as metallization, to provide electrical contact between layers of wiring levels. In the dual damascene process, the via openings and die wiring pattern openings are both provided in the dielectric layer before filling with fee conducting metal. The dual damascene process can simplify the manufacturing process by eliminating some internal interlaces. Damascene processing followed by metallization is continued for each layer in the electronic component until the electronic device is completed.
Barrier layers are often needed between the dielectric material and the conductive material in order to prevent atoms of the conductive material from diffusing into and at times through the dielectric material and into other active circuit device structures. Diffusion of conductive material in the device can cause inter-level or intra-level snorts through the dielectric material. Also, junction leakage can result, and threshold voltage (Vt) levels of the transistors formed within the substrate can shift. In some-cases, device functionality can be destroyed.
Diffusion is a particular concern when a high diffusivity element is used as a conductive material in the semiconductor structures. For example copper atoms often exhibit relatively high diffusion mobility in most dielectric materials. Yet, in spite of this problem, copper is a favored material for interconnects because of its superior conductivity.
FIGS. 1A and 1B are representational cross-sectional views of process steps taken to provide a copper interconnect of die prior art. With reference to FIG. 1A, a dual-damascene copper interconnect is represented, which includes trench 16 and via 17, copper line 12 embedded in dielectric 10, cap layer 14 (e.g. silicon nitride, silicon carbide, or silicon oxide) and interlayer dielectric 15. As shown, via 17 is etched in the interlayer dielectric 15 and the cap layer 14 to expose copper line 12. Typically, a barrier layer (e.g. tantalum, tantalum nitride) is deposited on the patterned interlayer dielectric using a PVD process. A copper seed layer is then deposited over the barrier layer, followed by a Cu plating process to fill the trench 16 and via 17 with copper 18 as shown in FIG. 1B.
Misalignment of one patterned interlayer over another interlayer each with its embedded, interconnect structures often leads to vias that do not fully land on the underlying conducting lines or conducting lines that do not fully land on the underlying vias. Unlanded vias and lines can significantly reduce electrical connection to the lower metallization and result in low process yield or in field failures. As a result, electronic circuits are designed with specific alignment tolerance values, for example, in 65 nm node technology, via diameter is about 100 nm and the overlay budget is about 40 nm. Therefore, there is an interest to provide interconnect structures with relaxed manufacturing tolerance values, particularly for high-density wiring designs.